In the prior art, integrated circuit memory devices have been developed which store data for indefinite periods of time in the absence of electrical power being applied thereto and which also have the capability of selectively changing or programming the data stored therein. Of particular interest herein is a nonvolatile memory cell which utilizes a floating gate as the nonvolatile element. See e.g., U.S. Pat. No. 4,314,265 which discloses a four polysilicon layer, floating gate nonvolatile memory cell, and U.S. Pat. No. 4,274,012 which discloses a three polysilicon layer, floating gate nonvolatile memory cell with substrate coupling. Either of these nonvolatile memory cells may be arranged, as is known in the art, to construct nonvolatile random access memories (NOVRAM's) and electrically erasable programmable read only memories (EEPROM's). See, e.g., U.S. Pat. No. 4,300,212, which discloses a NOVRAM device and U.S. Pat. No. 4,486,769, which discloses an EEPROM device. Of course, the principles of the present invention are applicable to other devices utilizing floating gate technology.
In U.S. Pat. No. 4,274,012 for example, the disclosed nonvolatile memory cell has three layers of polysilicon, each layer being generally electrically isolated from the substrate and each other. The first polysilicon layer is a programming electrode. The second polysilicon layer is the floating gate. The floating gate has a portion capacitively coupled to the programming electrode to form a programming tunneling region in which electrons tunnel from the programming electrode to the floating gate. Another portion of the floating gate is capacitively coupled to a n-implant region in the p-type substrate. The n-implant region is a bias electrode. The third polysilicon layer, which is an erase/store electrode, is capacitively coupled to a portion of the floating gate to form an erase tunneling region in which electrons tunnel from the floating gate to the erase/store electrode. Another portion of the erase/store electrode is capacitively coupled to the bias electrode in the substrate.
To initiate tunneling, a high potential, such as 25 v, is applied to the erase/store electrode while the programming electrode is held at a low potential, such as ground. The substrate bias electrode is caused to be held either at the low potential of the programming electrode or held at the high potential of the erase/store electrode, depending on whether electrons are to be tunneled from or to the floating gate, respectively. With the bias electrode held at the high potential, the floating gate being strongly capacitively coupled to the bias electrode is elevated to the high potential. Therefore, high potential exists across the programming tunneling region between the programming electrode and the floating gate so that electrons are tunneled onto the floating gate. Conversely, with the bias electrode held at the low potential, the floating gate will also be at the low potential because of the strong capacitive coupling to the bias electrode. Therefore, high potential exists across the erase tunneling region between the floating gate and the erase/store electrode. Electrons will then tunnel from the floating gate to the erase/store electrode.
The above-described nonvolatile memory cell, in one useful application, forms the nonvolatile portion of a NOVRAM memory cell disclosed in U.S. Pat. No. 4,300,212. The volatile portion of the NOVRAM memory cell is addressed, read from and written to in a manner known for MOS flip-flop type memory cells. The nonvolatile portion of the NOVRAM memory cell is coupled to the data and inverse data nodes of the volatile portion of the NOVRAM memory cell. The bias electrode is connected to the drain of an enhancement mode transistor with a grounded source. The data node of the volatile portion of the NOVRAM memory cell is coupled to the gate of this transistor. When the data node is at zero volts, representing one binary state, the transistor is turned off allowing the bias electrode to be at a floating potential. The bias electrode is further capacitively coupled to the erase/store electrode. Application of the high voltage store pulse to the erase/store electrode will cause the potential of the bias electrode to be elevated to the high potential. Electrons will then tunnel from the programming electrode to the floating gate, as described hereinabove, giving it a net negative charge. Conversely, when the data node is at 5 volts, representing the other binary state, the transistor is turned on thereby coupling the bias electrode to zero volts. Application of the high voltage pulse to the erase/store electrode will cause electrons to be removed from the floating gate by tunneling to the erase/store electrode, as described hereinabove, leaving a net positive charge thereon. Therefore, the charge of the floating gate stores the state of the data node of the volatile portion of the NOVRAM cell when the high voltage pulse is applied to the erase/store electrode.
To sense the charge on the floating gate, the floating gate forms the gate of an enhancement mode sense transistor. The drain of the sense transistor is coupled to the inverse data node of the volatile portion of the NOVRAM memory cell. The sense transistor is turned on when the floating gate has a net positive charge and is turned off when the floating gate has a net negative charge. Thus, the charge stored on the floating gate may be determined from the on or off state of the sense transistor and the potential of the inverse data node set therefrom upon power up of the NOVRAM device.
The nonvolatile memory cell described in U.S. Pat. No. 4,274,012, in another useful application, is used in the construction of each memory cell in an array of cells of an EEPROM device as disclosed in U.S. Pat. No. 4,486,769. In the array disclosed in this patent, the erase/store electrode is common to each cell in a column, and the programming electrode is common to each cell in a row. Furthermore, the bias electrode in each cell along a row are electrically connected to each other. To select one cell in the array, the programming electrode across the row in which the selected cell is located is held to a low potential, such as 0 volts and the erase/store electrode of the column in which the selected cell is located is raised to a high potential, such as 36 volts. The programming electrode in all other rows is raised to an intermediate potential, such as 26 volts and the erase/store electrode in all other columns is held to a low potential, such as 0 volts. The bias electrode for each cell in the row of the selected cell is driven to either the intermediate potential or the low potential, depending on whether the floating gate of the selected cell is to be programmed or erased, respectively. The bias electrode for cells in all other rows is driven to the intermediate potential. As described in the '769 patent, the full potential difference between the low and high potentials will exist across either the programming tunneling element or the erase tunneling element in the selected cell as a function of the bias electrode potential. Electrons will then tunnel across the selected tunneling element.
In all other cells along the row of the selected cell in this prior art EEPROM device, a potential difference exists across the tunneling element between its programming electrode and floating gate. The intermediate voltage applied to the bias electrode of the unselected cell is partially coupled to the floating gate while the programming electrode is held at the low potential. Since the unselected cell's erase/store electrode is also held to zero volts, the capacitive coupling between the erase/store electrode and the floating gate prevents the floating gate from having the same voltage as the bias electrode. Thus, when the capacitive relationships are selected as describe in the '769 patent, the floating gate in each of the cells in the row of the selected cell will not have a potential sufficient to initiate tunneling of electrons to the floating gate.
Similarly, a potential difference will exist across the tunneling region between the erase/store electrode and floating gate of all other cells in the column of the selected cell. Since the bias electrode and programming electrode of all nonselected cells in this column are at the intermediate potential, their floating gates will also have a potential near the intermediate potential. The erase/store electrode of these selected cells in the column will be at the high potential. The resultant potential difference across the erase tunneling region is therefore insufficient to cause elections to tunnel from the floating gate.
In each cell of this EEPROM device, a pair of transistors are coupled to the channel region of the substrate adjacent the floating gate. The gate of each of these transistors is formed from the erase/store electrode. Data potential is coupled to the channel region through one transistor and bias electrode potential is coupled to the channel region through the other transistor. To erase the floating gate, both the data potential and the bias electrode potential are at the low potential. To program the floating gate, both the data potential and the bias electrode potential are at the intermediate potential.
The above approach has several limitations. First, a number of capacitance interrelationships and tunnel voltage requirements must be maintained in order to avoid data disturbs of unselected cells during a write operation. In addition, logistical requirements of arrayed cells can make a single cycle write operation difficult to implement in practice. Consequently, in practical operation, before the floating gate is programmed, each EEPROM cell is first erased. Thus, each write cycle to a memory cell is preceded by an unconditional erase cycle, incurring unnecessary write time and cell wear out.
It is desirable to increase the number of memory devices which are fabricated from a single wafer to increase the chip yield per wafer and thereby to reduce the cost of each chip. In this regard, the size of each memory cell within the memory device must be reduced. However, such reductions in size do not allow a simple miniaturization of existing memory cells. For example, tolerances between mask levels may be difficult to maintain or the miniaturized design may require minimum channel widths not compatible with existing technology. Miniaturization of the above-described nonvolatile memory cell does not allow the necessary capacitive values and relationships to be maintained for an operational memory device. For example, should the required capacitive relationships in the EEPROM device described in the '769 patent not be maintained, the voltages described as occurring across the tunneling regions of unselected cells in the row and columns of the selected cell may be sufficient to cause inadvertent tunneling or a data disturb of the unselected cell. Furthermore, the overhead requirements of a separate and distinct bias electrode region for a write operation, and floating gate channel region for a read operation, combined with the aforementioned inherent tolerance requirements needed to prevent disturb conditions, makes shrinking of present memory cells for very high density applications impractical.
It is also desirable to eliminate one or more of the above-described capacitive couplings in the NOVRAM device. Such capacitive couplings introduce losses in obtaining the voltage relationships necessary to induce tunneling of electrons between the polysilicon layers. Eliminating such capacitors, therefore, would improve device operation. Furthermore, the elimination of these capacitances enables a greater degree of miniaturization, since the need for the large amount of chip real estate required to form such capacitors would be eliminated.
Furthermore, device operation and cell dimensions could be optimized by reducing component count in each memory cell and reducing the number of cycles required for a write operation. For example, in the EEPROM device, it is desirable that a write cycle (programming the floating gate) be accomplished in a single cycle obviating the need for an unconditional erase prior to each write cycle.